//In this stage: exp tweak and rounding will be proceed
//output is the eventual result of FP calculation
//ATTENTION: sign&exp signals must add S1 dummy DFF to sustain uniform 3-stage pipeline
module fpu_s2
#
(
    parameter length_exp=11,
    length_val=52,
    msb_op=length_exp+length_val,
    length_mdiv=2**($clog2(length_val)),
    mdiv_dummy=length_mdiv-length_val
)
(
    input [length_val+3:0]fadd_addresult,
    input [2*length_val-1:0]fmul_mulresult,
    input fadd_sign,
    input [length_exp-1:0]fadd_expin,
    input fmul_sign,
    input [length_exp:0]fmul_expin,
    input [2:0]rounding_mode,
    output [msb_op:0]fadd_fpout,
    output [msb_op:0]fmul_fpout

);
wire [length_exp+1:0]fadd_adj_exp;
wire [length_exp+1:0]fadd_align_exp;
wire [length_val-1:0]fadd_adj_val;
wire [length_val+1:0]aout;
defparam FADD_ALIGNER.result_width=length_val+4;
defparam FADD_ALIGNER.normalize_width=length_val+2; //+2bit for rounding
normalize_shifter FADD_ALIGNER
(
    .datai(fadd_calc),
    .left_shift_num(fadd_align_exp),
    .datao(aout)
);
defparam FADD_ROUNDER.length_val=length_val;
fpu_rounder FADD_ROUNDER
(
    .fp_sign(fadd_sign),
    .roundmode(rounding_mode),
    .datai(aout),
    .datao(fadd_adj_val)
);
//assign fadd_align_exp={};
assign fadd_fpout={fadd_sign,fadd_adj_exp[length_exp-1:0],fadd_adj_val};
//TODO FADD/FMUL actually still needs post-calc 0/inf detect and export
//i.e. early detection of 0/Inf may not be correct 
wire [length_exp+1:0]fmul_adj_exp;
wire [length_val-1:0]fmul_adj_val;
wire [length_val+1:0]mulval_o;
defparam FMUL_ALIGNER.result_width=length_mdiv;
defparam FMUL_ALIGNER.normalize_width=length_val+2;
normalize_shifter FMUL_ALIGNER
(
    .datai(valmul),
    .left_shift_num(mexp_align),
    .datao(mulval_o)
);
defparam FMUL_ROUNDER.length_val=length_val;
fpu_rounder FMUL_ROUNDER
(
    .fp_sign(fmul_sign),
    .roundmode(rounding_mode),
    .datai(mulval_o),
    .datao(fmul_adj_val)
);
assign fmul_mulresult = {fmul_sign,fmul_adj_exp,fmul_adj_val};

endmodule